| 摘要 |
PURPOSE:To realize the efficient processing and the increase in the calculation speed by means of a digital circuit by calculating a quantization step width in one block by an arithmetic equation of (maximum value - minimum value)/2<n> and dividing the signal into 2<n>+1 sets of sections based on nearly a median of the step width. CONSTITUTION:A block data outputted from a data delay section 105 is divided into a prescribed section based on a maximum value from a maximum value detection section 103 and a minimum value of a minimum value detection section 104 by a division conversion section 106. The calculation of a split section width St is realized by only the subtraction of the maximum value and the minimum value and the division of the power of 2. The split section width St is divided into 2<n>+1 sections and to which section each sample belongs is expressed by 2<n>+1 kinds of normalized codes C0-C2<n> per one sample. Simultaneous vector quantization is applied to a 16-dimensional space assembling 16 samples, for example, and the data of ls samples is expressed by a code block in, e.g., 8-bit. |
