发明名称 DIGITAL PLL CIRCUIT
摘要 <p>PURPOSE:To reduce a initial pull-in time by detecting the start of an input signal at the initial puling in, generating a pulse at a signal start pulse generating circuit at the start of the input signal, and setting a frequency divider to a prescribed state. CONSTITUTION:When a signal start pulse generating circuit 11 monitors an input signal and detects the input signal, generates an input start pulse whose pulse width T=1/2fnfo at the top of the input signal. Frequency dividers 1, 2 are set to the state of n/2 while a pulse is inputted to a set input. For example, if the phase of an input signal Si is deviated from the phase of an output signal So by 180 deg., and the input signal Si is inputted, the signal start pulse generating circuit 11 generates a pulse (a) to set the frequency divider 12 to n/2=2 in the case of the frequency division ratio of the frequency divider set to 4(n=4) and the phase split number set to 8(N=4). In such a case, the phase locking is immediately taken and the initial pull-in time is made zero.</p>
申请公布号 JPH0292021(A) 申请公布日期 1990.03.30
申请号 JP19880242472 申请日期 1988.09.29
申请人 MITSUBISHI RAYON CO LTD 发明人 OKADA HIROSHI;SAITO NORIAKI;AKAHA HIDETOMO;TASHIRO SHINTARO
分类号 H03L7/06;H03L7/081;H03L7/099;H04L7/00;H04L7/033 主分类号 H03L7/06
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