| 摘要 |
PURPOSE:To reduce the fluctuation of an output logic level by providing a logic level compensation circuit using a connecting point among a resistance load type differential input circuit, a 1st field effect transistor(TR) and a differential input circuit as output terminal and suppressing the fluctuation of the input logic threshold level. CONSTITUTION:If an input logic level is lowered in a logic level shift circuit, the potential of gate electrode of a current source FET Q6. Then a current flowing to a logic level shift circuit is decreased. Thus, the gate source voltage of a source follower FET Q5 of the logic level shift circuit is decreased, the potential at an output terminal 3 is compensated to be nearly constant. Moreover, if the diode characteristic of diodes D5, D6 of the logic level shift circuit is fluctuated and a voltage Vf is decreased, the output potential of a compensation circuit is increased thereby increasing the current of the logic level shift circuit. Then a gate-source voltage of the FET Q5 is increased and the potential at the output terminal 3 is compensated to be nearly constant. |
