| 摘要 |
PURPOSE:To improve the wiring efficiency by installing many wiring channels in wiring areas near the centers of two or more divided areas on a semiconductor substrate while a few in wiring areas distant from said centers. CONSTITUTION:Element areas C1-C9 to wire gates and element areas G1-G8 to wire elements in the gates are arranged alternately in the wiring layer 2 of a semiconductor substrate 1. The wiring areas C1, C5, and C9 on both sides of areas divided into two pieces on the semiconductor substrate each have three wiring channels C11-C13, C51-C53, and C91-C93, the wiring areas C2, C4, C6, and C8 near the centers of said areas divided into two pieces each have four wiring channels C21-C24, C41-C44, C61-C64, and C81-C84, and the wiring areas C3 and C7 at the centers of said areas divided into two pieces each have five wiring channels C31-C35 and C71-C75. Many wiring channels are installed in more congested wiring areas, therefore, the utilization efficiency of the wiring areas C1-C9 is evened out to enable efficient wiring. |
