发明名称 SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To reduce the degree of increase of power supply currents di/dt and to suppress the fluctuation of standard voltage wiring on a semiconductor substrate by providing a transistor between an output terminal and a power supply, and providing a circuit which delays only when this gate voltage changes from a high level to a low level. CONSTITUTION:By B7 becoming a low level P7 becomes ON and N7 becomes OFF, and output 07 discharges electricity from a low level to a high level. The charge currents at this time becomes half as gm of P7 is set to half the conventional one, and di/dt also becomes 1/2. Pb7 is off until F7 becomes a low level, and the difference of time for B7 and F7 to become low levels is determined by the switching speeds of IA7 of IB7 and can be set easily. When Pb7 becomes on at which F7 becomes a low level, the di/dt of P7 is rapidly nearing to 0, and even if Pb7 is turned ON and di/dt becomes great, the total di/dt becomes half the conventional one. This way, by making di/dt small, the fluctuation of VCC-r becomes small, and malfunction becomes hard to occur.</p>
申请公布号 JPH0289373(A) 申请公布日期 1990.03.29
申请号 JP19880241920 申请日期 1988.09.27
申请人 NEC CORP 发明人 WATANABE TAKESHI
分类号 G11C17/00;G11C7/00;G11C11/409;G11C16/06;G11C17/18;H01L21/822;H01L21/8247;H01L27/04;H01L27/10;H01L29/76;H01L29/772;H01L29/788;H01L29/792 主分类号 G11C17/00
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