发明名称 |
BINARY CALCULATING CIRCUIT |
摘要 |
PURPOSE: To accelerate carry propagation and speed up calculation by changing the roles between a 2nd input signal and a carry-in input signal. CONSTITUTION: A 1st means 100A of an adder 2A generates an exclusive OR signal Ai(+)Ri-IS between a 1st input signal Ai and the carry-in signal Ri-1S and a 2nd means 200A execute the exclusive OR function between the signal Ai(+)Ri-1S and its complementary signal/(Ai(+)Ri-1S) and a 2nd input signal Bi and generates a result signal Si. Then a 3rd means 300A generates a carry- out signal RiS by a transmitting function consisting of two transmission gates controlled with the signal Ai(+)Ri-1S and its complementary signal/[Ai(+)Ri-1S]. Thus, the roles of the 2nd input signal Bi and carry-in signal Ri-1S are exchanged and the carry-out signal RiS is calculated by using the intermediate variable obtained by the exchanging, thereby greatly reducing the carry propagation delay of parallel-connected cells. |
申请公布号 |
JPH0289130(A) |
申请公布日期 |
1990.03.29 |
申请号 |
JP19880238613 |
申请日期 |
1988.09.22 |
申请人 |
CENTRE NATL ETUD TELECOMMUN <PTT> |
发明人 |
HEDEI IMIDA;PIEERU DEYUAMERU |
分类号 |
G06F7/38;G06F7/50;G06F7/501;G06F7/503;G06F7/506;G06F7/508;G06F7/52;G06F7/525;G06F7/527;G06F7/53 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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