| 摘要 |
PURPOSE:To attain high-speed access by dividing plural transistors connected to a word line into plural groups and connecting a subword line to be commonly connected for each group through an inverter to a main word line. CONSTITUTION:For plural transistors composed of transistors connected to a main word line 3, they are divided into plural groups 16-1 and 16-2, and subword lines 7-1 and 7-2 connected commonly for respective groups are connected through inverters 17-1 and 17-2 to the main word line 3. Consequently, a buffer 14 of the main word line 3 is sufficient to have an output capacity for driving only prescribed one group. The inverters 17-1 and 17-2 are sufficient to be small for driving only the total of the memory cells. Thus, the access time can be shortened. |
