| 摘要 |
PURPOSE:To facilitate the working of a gate electrode wiring by arranging the connection part of gate electrodes of adjacent cells for connecting word lines so as to be positioned in the vicinity of the surface of a trench. CONSTITUTION:A buried layer 5 is formed in a silicon substrate 1, and a silicon oxide film 211 is formed; then a silicon nitride film 22 and a silicon oxide film 23 are deposited one after another by CVD method, and these are patterned in the form of an island; a trench 2a is formed by reactive ion etching, and an thermal oxide film 212 is formed on the side wall of the trench; then a silicon nitride film 24 is deposited, and is left only on the trench side wall; a trench 2b is formed; AsSG is deposited on the whole surface, arsenic is diffused and, an N<-> type layer 6 is formed; after a thermal oxide film is formed on the inner wall of the trench 2b, a trench 2c is formed by etching the substrate surface; a silicon oxide film is deposited on the whole surface, and left, as an insulating film 4, only in the trench bottom; after an insulating film 7 is formed on the surface of the N<-> type layer 6, and electrode 8 is buried; the silicon nitride films 22, 24 and the silicon oxide films 211, 212 are eliminated; after a gate insulating film 9 is formed, a polycrystalline silicon film 10 is deposited, and an electrode 10 is formed; the substrate surface is exposed, arsenic is ion-implanted, and an N-type layer 11 is formed; then the surface is covered with an insulating film 12, a hole is formed, and a bit line 14 is arranged. |
