| 摘要 |
PURPOSE:To decrease the hardware quantity without deteriorating the computing accuracy by generating a K-bit for single accuracy from the added data. CONSTITUTION:A shift value generating circuit 1 produces the shift value of the data on the digit matching shifters 2 and 2a. The double precision K-bit generating circuits 3 and 3a include no single precision circuit. An adder 4 performs the addition including the bits (g), (r) and K. A single precision K-bit generating circuit 5 produces the bits (g), (r) and K of the intermediate result of addition from the outputs of the adder 4 in the case the input data has the single precision. Then the bits set at the positions of the bits (g) and (r) of the single precision are used directly as the bits (g) and (r) of the intermediate result of the single precision. While the K-bit of the intermediate result of the single precision is obtained by applying an OR to the position of the K-bit of the single precision through the K-bit of the double precision. Thus the K-bit generating circuit for single precision can be omitted for the digit matching shift. Then the digit matching is attained for all data with the double precision. |
