| 摘要 |
Device for reducing losses from analog memories using sample-and-hold circuits. This analog memory comprises a first sample-and-hold circuit 10 connected to an inverting second sample-and-hold circuit 30. The inverting second sample-and-hold circuit 30 is connected to an inverting amplifier circuit 4. A circuit 50 carrying out a summation is connected, on the one hand, via an input E7 to the output S4 of the inverting amplifier circuit 40 and, on the other hand, via an input E6 to the output S1 of the first sample-and-hold circuit 10. The signal delivered during the off time of the sample-and-hold circuits 10, 30, on an output S6 of the circuit 50 carrying out a summation, is proportional to a signal to be stored delivered on an input of the first sample-and-hold circuit 10. <IMAGE>
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