发明名称 NETWORK SYNCHRONIZATION CLOCK SELECTION CIRCUIT
摘要 <p>PURPOSE:To minimize the self-running state of an exchange and to suppress the occurrence of an error in data communication or the like by detecting a clock error and outputting a network synchronization clock of the most significant station from other selector while a selection output of one selector is shifted periodically. CONSTITUTION:Suppose that a selector 1 selects a network synchronizing clock of the most significant station C, a control circuit 5 executes the acquisition of synchronizing clock selected by a selector 1 by a PLO 31 to keep the state and the result is outputted. When a frequency comparator 32 or a clock interruption detection circuit 33 detects it, the control circuit 5 detects it that the network synchronizing clocks B, D do not cause a clock error signal even through a selector 2, a frequency comparator 42, a clock interruption detection circuit 43 and an OR gate 44 and applies selection control such that a clock B is selected, a network synchronization clock B is outputted from the selector 1 so as to perform the acquisition of synchronism with the PLO 31.</p>
申请公布号 JPH0282833(A) 申请公布日期 1990.03.23
申请号 JP19880235356 申请日期 1988.09.20
申请人 FUJITSU LTD 发明人 FUKUDA KEIJI;ABE MASATOSHI
分类号 H04L7/00 主分类号 H04L7/00
代理机构 代理人
主权项
地址