| 摘要 |
<p>PURPOSE:To suppress increase in a circuit scale by applying control to a state data corresponding to each of plural time division signals while being stored in a state data temporary storage means. CONSTITUTION:Time division is applied while a state ABCD corresponding to each of 10 lines and an enable signal EN are stored. The state ABCD and the enable signal EN outputted from a 1st cycle ROM 11 give a RAM write address 19 corresponding to a channel CH0 to the RAM 12 while an address generator 15 activates a write enable signal WE. Thus, an output from the ROM 11 in the channel CH10 is stored in a corresponding address in the RAM 12. The operation above is applied in time division at every channels CH0-CH9 to apply synchronization protection at every line.</p> |
