| 摘要 |
PURPOSE:To reduce an area occupied by a gate electrode of a MISFET for memory- cell selection use and by a word line and to enhance an integration density of a semiconductor memory device by a method wherein the gate electrode (and the word line) are formed inside a narrow groove in self-alignment with the groove. CONSTITUTION:A memory cell 11 is constituted in an active island region 3 whose circumference has been surrounded by a narrow groove 2 and on its side wall; an extension direction of a complementary data line DL of this narrow groove 2 is set to a wide groove-width size WD and an extension direction of a word line WL is set to a narrow groove-width size WW. A MISFET QS for memory-cell selection use of the memory cell M is formed on a main face of the active island region 3 and at the upper part of a side wall of the active island region 3; it is constituted mainly of a semiconductor substrate 1, a gate insulating film 9, a gate electrode 10, one pair of n<+> type semiconductor region and n<-> type semiconductor region 11 as a source region and a drain region. The gate electrode 10 is formed in self-alignment with the active island region 3 and the narrow groove 2. Thereby, an area of the memory cell M can be reduced by an amount corresponding to an area occupied by the gate electrode 10 and to a mask-alignment margin area in a manufacturing process; an integration density of a DRAM can be enhanced. |
