| 摘要 |
PURPOSE:To allow the application of the data driver to sequential and simultaneous sampling and to contrive the lowering of an operating speed and the reduction of electric power consumption by branching the output signal of a shift register to 3 signals and selecting these signals with three control signals to form the sampling timing signals to be applied to a sample-hold circuit. CONSTITUTION:All of the three control signals are made into a '1', by which the simultaneous sampling of the R, G, B signals applied to the sample-hold circuit 5 is executed if a timing selection circuit 6 is constituted of, for example, an AND circuit. The sampling timing signals dividing the output signal of the shift register 4 to three timings can be formed by setting the timings of the three control signals and, therefore, the sequential sampling of the R, G, B signals is possible. The application of the data driver to both the sequential sampling and the simultaneous sampling is possible in this way; in addition, the operating speed of the shift register is lowered and the electric power consumption is reduced. |
