发明名称 Floating point processor - has adder subtractor handling exponent part for improved execution of multiplication and division
摘要 A floating point computer has part product registersa (10, 11), a shaft register (20), a multiplier register (40), a value selection circuit (50), a shaft unit (60) for a 4 bit multiplier move, 8 bit registers (70, 80), a processor (90) for the exponent values and a counter (100) coupled to an EXCLUSIVE-OR (110). The processor (90) provides addition and subtraction of the data as well as providing handling of the multiplication and division values. The unit operates together with a processor (21) that has an output word length greater than that of the input. ADVANTAGE - Improves processing speed of floating point multiplication and division.
申请公布号 DE3931545(A1) 申请公布日期 1990.03.22
申请号 DE19893931545 申请日期 1989.09.21
申请人 HITACHI, LTD., TOKIO/TOKYO, JP 发明人 KUME, MASAJI, HADANO, JP
分类号 G06F7/487;G06F7/57 主分类号 G06F7/487
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