| 摘要 |
<p>PURPOSE:To detect all bus hang states without impairing the burst transfer and to surely reset a data processing system by using a 2nd resetting circuit to monitor the production of the bus grant signals within a fixed time and to produce a resetting signal. CONSTITUTION:The masters 3 and 5 are connected to a memory 4 via a bus 7, and a bus arbitration circuit 2 produces a grant signal to a bus request signal and then produces a system resetting signal to permit the use of the bus 7. A request generating circuit 10 produces a request signal to the circuit 2 with a resetting instruction. In a bus hang state, however, no bus grant signal is outputted for a fixed period against the production of a bus resetting request. A 2nd resetting signal generating circuit 18 monitors the production of grant signals for a fixed time and produces a resetting signal. In this case, the fixed time is set longer than the bust transfer time and therefore the bus hand state is detected and can be reset without mistaking the normal burst transfer for a bus hang.</p> |
