| 摘要 |
<p>In a computer system, a CPU bus cycle control section (211) receives a bus cycle request (BC-REQ) to generate a system bus request (SBC-REQ) and feeds back a ready notice (READY-a) to the CPU (11). A system bus cycle control section (221) performs the bus cycle control in response to the system bus cycle request (SBC-REQ) from the control section (211) and generates a ready notice (READY-b) to the CPU bus cycle control section (221). The computer system includes a timer (213) for delaying the ready notice (READY-b), a selector (214) for selecting one of the ready notice (D'READY) delayed by the timer (213) and the ready notice (READy-b) from the system bus cycle control section (221) and supplies the selected ready notice to the CPU bus cycle control section (211) and a register (212) for holding a recovery state bit FRDY and recovery time data.</p> |
