| 摘要 |
<p>A memory cell array includes static memory cells arranged in an array of n rows x m columns. Each of the memory cells includes MOS transistors formed in a semiconductor substrate (11) and in a corresponding one of well regions (12-1, 12-2, ---, 12-n) of the conductivity type opposite to that of the semiconductor substrate (11). The well regions (12-1, 12-2, ---, 12-n) are independently formed for each row or for every two or more rows of the memory cell array. The well regions (12-1, 12-2, ---, 12-n) are connected to the respective sources of MOS transistors formed in the well regions (12-1, 12-2, ---, 12-n). The source and back-gate of each of the MOS transistors formed in the well regions (12-1, 12-2, ---, 12-n) are connected to the common source wirings (14-1, 14-2, ---, 14-n) for each of the independently formed well regions (12-1, 12-2, ---, 12-n). Isolation circuits are respectively connected between the common source wirings (14-1, 14-2, ---, 14-n) for the respective well regions (12-1, 12-2, ---, 12-n) and the power source. A row of the memory cell array to which a defective memory cell is connected is isolated from the power source by means of the isolation circuits.</p> |
