发明名称 CONTROL SYSTEM FOR PLL CIRCUIT
摘要 PURPOSE:To improve high speed performance for establishing synchronization and stability in a steady-state by varying a conversion gain coefficient of a phase comparator section in multistage from a larger to a smaller coefficient according to the elapse of time and varying the loop gain of a loop filter section from a smaller to a larger gain according to the change in the conversion gain coefficient. CONSTITUTION:The system consists of a phase comparator section 1, a loop filter section 2 and a digital VCO section 3. The conversion gain coefficient K1 of a multiplier 1-2 in the phase comparator section 1 is changed from a larger value to a smaller value as the elapse of time and the loop filter 2 is provided with a multiplier 2-3 and an adder 2-4 to change the loop gain K2 from a small to a large value corresponding to the change in the conversion gain coefficient K1. Thus, the high speed performance for establishing synchronization and the stability in the steady-state obtained by controlling the gain conversion characteristic K1 are further improved.
申请公布号 JPH0275223(A) 申请公布日期 1990.03.14
申请号 JP19880226536 申请日期 1988.09.12
申请人 OKI ELECTRIC IND CO LTD 发明人 ONISHI KAZUMI
分类号 H03L7/107;H04L7/033 主分类号 H03L7/107
代理机构 代理人
主权项
地址