| 摘要 |
<p>PURPOSE:To read at high speed by making variable the on-resistance of a load transistor under the condition of reading. CONSTITUTION:When data change from '0' to '1' and a current starts to flow from a bit lien BL, the potential of the bit line BL is decreased, a node N1 turns to be a higher level to be determined by the ratio of the on-resistance of transistors (TR) Q1 and Q2 and turns on TR Q3 and Q4 for feedback. In this case, a voltage between the source gates of load TR Q5 is dropped and the on-resistance is increased. On the contrary, when the data change from '1' to '0' and the current stops flowing from the bit line BL, the potential of the line BL is increased, the node N1 turns to be a lower level to be deter mined by the on-resistance of the TR Q1 and Q2 and turns off the TR Q2 and Q4 for feedback. In this case, the source gate voltage of the TR Q5 is increased and the on-resistance is lowered. Consequently, the node N2 can be charged form the potential of the line BL to a current voltage terminal Vcc level within the short period of time. Thus, the high speed reading can be executed.</p> |
