| 摘要 |
<p>PURPOSE:To surely demodulate and reproduce a data signal even when the data signal arrives in burst wave shape by reading the data signal by a clock signal generated by setting the leading or trailing pulse edge of a demodulated data signal as reference synchronizing with the clock signal written on a memory once and decided after delay of prescribed time. CONSTITUTION:At a memory circuit 20, demodulated data D1 is written on an address 0 and demodulated data D2 on an address 1 sequentially synchronizing with the clock signal from a first frequency division circuit 15, respectively, after a write start pulse signal is supplied from a write pulse generation circuit 19 to a write designation terminal (WRES). ln such a case, the write start pulse signal from the write pulse generation circuit 19 is delayed by a time T of several bits via a delay circuit 21, and is supplied to the readout designation terminal (RRES) of the memory circuit 20 as a readout start pulse. in such a way, it is possible to obtain the demodulated data signal without including jitter preventing the jitter included in the demodulated data from being included in the readout clock.</p> |
