| 摘要 |
PURPOSE:To generate a desired signal by providing a clock generator and reading out a desired timing signal written in advance in a ROM synchronously with a counter. CONSTITUTION:When a clock generator 1 outputs a clock, a counter 2 operates synchronously with the clock. The counter 2 is connected to address terminals 31, 38 of a ROM 3, and write data of the ROM 3 is outputted successively by synchronizing with an operation of the counter 2. In this cased, a desired timing signal is applied to each data bit of the ROM 3, and timing data is written in the ROM 3 in advance. When the generator 1 outputs the clock, the counter 2 operates. By synchronizing with this operation, the data of the ROM 3 is read out, and the desired timing signal can be generated easily. Also, by changing the storage contents of the ROM 3, the timing signal can be changed easily. |
