发明名称 Memory organization and output sequencer for a signal processor
摘要 A specialized tone receiver is capable of detecting tones on many different digital signal channels simultaneously. A single memory is used to buffer incoming digital signals. Independent write and read sequencers write samples into and read samples from the buffer memory, respectively. The write sequencer writes all samples corresponding to a given sample time at essentially the same time, while the read sequencer reads out all of the samples corresponding to a given channel of interest in reverse sequential chronological order (i.e., in the opposite order from the order the samples were written) beginning with the most current sample. A priority structure controls access to the buffer memory, with the read sequencer being granted a higher access priority than the write sequencer. A filtering algorithm symmetrical in time and executed by a digital signal processor controlled by the same microcode sequencer which controls the read sequencer is used to detect specific frequencies present in the read channel samples. A separate, slower processor performs time validation functions on a time scale which is extremely slow compared with the time scale at which frequency validation is performed. The specialized tone receiver is extremely fast, requires only a single, relatively small input buffer memory (e.g., 128K bytes for a 512 channel PCM bus), and is capable of detecting several different specialized signalling tones on all of the channels of a multiport mulitchannel PCM bus in very close to real time.
申请公布号 US4908825(A) 申请公布日期 1990.03.13
申请号 US19880179269 申请日期 1988.04.08
申请人 NORTHERN TELECOM LIMITED 发明人 VEA, MATTHEW J. J.
分类号 H04Q1/457 主分类号 H04Q1/457
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