| 摘要 |
Registered output circuitry for a memory device includes a first latch which stores data from a sense amplifier on the rising edge, and outputs it on the falling edge, of the falling edge of an &upbar& O signal. This data stored in the latch is provided as output of only y, during the preceding rising edge of the &upbar& O signal the &upbar& C signal to the memory device was a logical 0 level, and the &upbar& W signal was a logical 1 level. Since the falling edge of the &upbar& O signal is the beginning of the memory cycle, the data at the output pin of the memory is the data read in the previous read cycle. This latency, however, enables a shortened average cycle time, and also provides registered outputs without the necessity of an external clock signal applied to the memory device.
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