| 摘要 |
PURPOSE: To secure charge equalization of a pair of signal lines by stopping the charge equalization of selected and divided memory sections more than one. CONSTITUTION: When memory sections which are divided more than one and given their address signals are selected, a section decipherment signal anti-SS1 falls to a low level in a section pre-decoder, a signal BLS is reversed to a low level via an inverter 11, NAND circuit NA1, and an inverter 13, and charge equalization of a pair of bit lines of BLn and an anti-BLn by transistors TR11-TR13 in a bit line equivalent circuit EQ1 is stopped. Similarly, charge equalization of a pair of data lines DLS and ant-DLS by a data line equivalent circuit EQ2 is stopped. Therefore, an operation of a selected memory section of which a signal line pair is sufficiently charged and equalized is secured. |
