| 摘要 |
PURPOSE:To avoid frame synchronization in erroneous timing by using a bit pattern different from each frame at the transmission side so as to send a frame synchronizing signal, extracting plural different bit patterns at the receiver side so as to detect the frame synchronizing signal. CONSTITUTION:A frame synchronizing signal (a) is inputted to synchronizing signal pattern generating circuits 1A, 1B generating different bit patterns to generate two kinds of bit patterns b, c respectively for each frame period, they are switched by a changeover circuit 3 and the result is sent to a multiplex circuit 5 as an output signal (e) alternately, the multiplexing circuit 5 multiplexes the signal onto an information signal (f) top add the frame synchronizing signal signal to form a transmission signal (g). At the receiver side, a bit clock recovery circuit 8 recovers the transmission signal (g) and when the bit patterns in the transmission signal are coincident with the bit patterns b, c at synchronizing signal pattern extraction circuits 9A, 9B, timing pulses j, k are outputted and a frame synchronization stabilizing circuit 17 establishes the frame synchronizing signal (s) based thereupon. Thus, the erroneous establishment of the frame synchronization due to a false frame synchronizing bit pattern is avoided. |
