发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To make possible the formation of an element in a smaller size and to contrive an increase in integration and a speedup by a method wherein an N-type buried layer under the base region of a lateral P-N-P transistor is raised higher than that under emitter and collector regions toward the surface of an epitaxial layer and is connected to the epitaxial layer. CONSTITUTION:A masking oxide film 2 is formed on a p-type Si substrate 1, the film 2 is selectively opened, an arsenic-silica glass is applied and a heat treatment is performed to form an n-type buried layer 3. After that, a part which serves as a base region of a lateral P-N-P transistor is again opened, arsenic is driven in using a resist 5 as a mask by an ion-implantation method and a heat treatment is performed. Thereby, the arsenic concentration in a partial region of the layer 3 becomes higher than that in the other region of the layer 3 and an n<++> buried layer 4 is formed. Then, an N-type epitaxial growth layer 6 is grown thereon. At this time, the layer 3 rises, but the region 4 highly doped with arsenic rises higher than that layer 3. Thereby, the connection of the region 4 with the layer 6 becomes certain and the improvement of the hfe-IC characteristics of the completed lateral P-N-P transistor can be attained.
申请公布号 JPH0271557(A) 申请公布日期 1990.03.12
申请号 JP19880146184 申请日期 1988.06.13
申请人 NEC CORP 发明人 TASHIRO TSUTOMU
分类号 H01L29/73;H01L21/331;H01L21/8228;H01L21/8229;H01L27/082;H01L27/102;H01L29/732 主分类号 H01L29/73
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