| 摘要 |
<p>PURPOSE:To enable a user to optionally stop the rise of a system by outputting a resetting signal to reset the system and continuing the stop state of the system rise while a reset key is depressed. CONSTITUTION:When a user depresses a reset key, a chattering absorbing circuit 11 outputs a resetting signal of a high level. A CPU 12 receives the resetting signal and starts an interruption process routine. When this process routine is through, a resetting pulse 12a is outputted to a clock input terminal of a latch circuit 13 from a resetting output terminal. When the pulse 12a is inputted to the circuit 13, the output of an output terminal Q is set at a high level. The output of the terminal Q is kept at a high level until a clear terminal CLR is set at a high level, and a resetting signal 13a is outputted to the CPU 12 and other devices respectively. Thus a system is totally reset.</p> |
