| 摘要 |
<p>PURPOSE:To maintain frame synchronism by outputting a stable regenerated clock signal in case of a burst error and inhibiting a frame period protecting circuit from operating, and attaining synchronization right after the error ends even if frame synchronism deviates within a specific range during the occurrence of the burst error. CONSTITUTION:When a burst error detections signal BDET is inputted to respective circuits, a clock signal regenerating circuit 21 outputs the stable regenerated clock signal CLOCK from the sample holding circuit in the circuit 21 although the burst error is occurring, and the frame synchronism protecting circuit 28 is inhibited from operating. Consequently, even when an error synchronism detection time is shortened, there is no disturbance of the burst error, and a frame synchronism window selecting circuit 27 selects a frame synchronism window signal WINDOW with specific bit length to make a return to a correct synchronizing phase right after the burst error ends even if the frame synchronism deviates within the specific range during the occurrence of the burst error.</p> |
