摘要 |
A computer system having a central processing unit, a dynamic memory controller, an error detection and correction network and a dynamic memory for storing data that are subject to being refreshed and to data bit errors. The dynamic memory controller has a refresh mode for controlling access to the memory only to refresh the data, a refresh with error detection and correction mode, for controlling access to the memory to merge or simultaneous refresh a row of data while detecting and correcting data bit errors, and a read/write mode for controlling access to the memory in response to CPU requests for a read/write memory operation. |
申请人 |
ADVANCED MICRO DEVICES, INC., SUNNYVALE, CALIF., US |
发明人 |
BRCICH, A., JOSEPH, SAN JOSE, CA 95132, US;LEVY, J., ROY, SUNNYVALE, CA 94087, US;MADEWELL, JIMMY, SAN JOSE, CA 95136, US;THREEWITT, BRUCE, N., LOS GATOS, CA 95030, US |