| 摘要 |
PURPOSE:To prevent occurrence of a shortage in capacity in a defect analyzing memory by providing an address detecting means, defective pattern detecting means, and write inhibit means. CONSTITUTION:At an address detecting means 60, a D type FF latches address signals given to a pattern memory 12 at every test cycle and an AND gate 62 performs coincidence detection by comparing the latched address signals in the preceding and succeeding test cycles. In a defective pattern detecting means 70, a D type FF 71 and AND gate 72 similarly detect the coincidence of defect occurring patterns in the preceding and succeeding cycles when an input is made from a logic comparison circuit 40. In a write inhibit means 80, outputs the detecting means 60 and 70 and the circuit 40 are supplied through an OR gate 53 and writing is selectively inhibited. When such constitution is used, data writing is inhibited when address signals supplied to the memory 12 are the same and, at the same time, defect occurring patterns are also the same in the preceding and succeeding cycles and, when a defect occurs due to the repeated impression of the same test pattern, writing in a defect analyzing memory 50 is performed one time only. Therefore, a shortage in capacity hardly occurs in the memory 50. |
