| 摘要 |
PURPOSE:To apply this controller to a high information processor having a high memory access frequency by providing the 3rd signal generating means generating a refresh operation end signal and a refresh address supply means supplied to a memory device. CONSTITUTION:A timing generating circuit 34 outputs a refresh start signal to a memory device by a refresh permission signal. Timing generating circuit 34 outputs a refresh operation end to an up-down counter 31 and a refresh address counter 33 when refresh is finished to the memory device. Then the refresh address counter 33 increments the count value by 1 to update the refresh address. On the other hand, the up-down counter 31 decrements 1 and the count value reaches ''0'', and a non-zero detection circuit detects ''0'', the timing generating circuit 34 makes a refresh request signal inactive by inactivating an output signal thereby avoiding refresh operation. |
