Data transfer control circuit.

摘要

A novel data transfer control circuit is disclosed in which a comparator (16) compares an output of a data transfer request signal pulse counter (9) with an output of a full adder (15) which is made up of a counter output of data transfer acknowledgement pulses plus a predetermined number of words by which a data transfer request signal pulse is capable of leading a data transfer acknowledgement signal pulse. This comparator is used to stop transmission of a data transfer request signal when the counter output of the data transfer request signal becomes equal to a full adder output represented by a counter output of a data transfer acknowledgement pulse plus a predetermined number of words by which the data transfer request signal pulse is capable of leading the data transfer acknowledgement signal pulse thereby to control the transmission of the data transfer request signal for data transfer in synchronous mode according to SCSI specification. A comparator for comparing the counter output of a data transfer request signal pulse with a counter output of a data transfer acknowledgement signal pulse is also used in such a manner that when the counter output of the data transfer acknowledgement signal pulse becomes equal to that of the data transfer request signal pulse, the transmission of the data transfer acknowledgement signal is stopped thereby to control the transmission of a data transfer acknowledgement signal pulse, thus controlling the transmission of the data transfer acknowledgement signal at the time of data transfer in an asynchronous mode of SCSI specification. When the circuit is set to the transmitting end of data transfer acknowledgement signal, the data transfer acknowledgement signal for the last transfer byte is held true at the time of data transfer in asynchronous mode of SCSI specification, and when data transfer in synchronous mode is decided for the next data transfer, the data transfer aknowledgement signal is rendered false after completely preparing for the next data transfer, thus preventing the data misfetching for the data transfer in synchronous mode.