发明名称 CONTROLLING CIRCUIT OF DIGITAL TELEVISION
摘要 PURPOSE:To facilitate an operation of the titled controlling circuit and to do suitably a diditization and integration of a household TV set, by inverting the highest bit of the control signal to perform the positive/negative controls and reducing the control width. CONSTITUTION:The output of a luminance control variable resistance 54 is fed to an A/D converter 52 via a signal line 53 in a luminance signal processing circuit. The converter 52 applies the control digital signal 51 of 4 bits to a control signal producing circuit 50 for complement of 2. The circuit 50 inverts only the MSB signal of the highest bit of the straight binary input signal and delivers the sine bit signal 49 of a multiplier 47. The signals 48 excepting the MSB signal is led to the multiplier 47 with no inversion. For the other input of the multiplier 47, the positive luminance signal 40 of 8 bits is obtained with the sine bit set at ''0''. Therefore the multiplier 47 multiplies the straight binary signal 40 by the complement signals 48 and 49 of 2 and delivers the prescribed result signal 45. As a result, the control width can be reduced for the control signal.
申请公布号 JPS58103281(A) 申请公布日期 1983.06.20
申请号 JP19810201524 申请日期 1981.12.16
申请人 TOKYO SHIBAURA DENKI KK 发明人 KUDOU YUKINORI;SUZUKI SUSUMU
分类号 H04N5/00;H04N7/00 主分类号 H04N5/00
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