发明名称 FREQUENCY SYNTHESIZER
摘要 PURPOSE:To prevent the occurrence of frequency variance at the time of frequency switching to shorten the output switching time by resetting a variable frequency dividing circuit so that the phase difference between the output signal of the variable frequency dividing circuit and a reference signal is about 0 at the time of frequency switching. CONSTITUTION:At the time of frequency switching, a setting circuit 7 sends a loop control signal to open a loop switch 10 and sets frequency division data corresponding to a desired frequency to a variable frequency dividing circuit 2. Simultaneously, the circuit 7 sends a reset signal to the variable frequency dividing circuit 2 with the reference signal as the trigger and sends a loop control signal to close the loop thereafter and equalizes the output signal phase of the variable frequency dividing circuit 2 and the reference signal phase to each other. Consequently, the frequency variance for frequency switching is eliminated. Thus, the output switching time is shortened.
申请公布号 JPH0267821(A) 申请公布日期 1990.03.07
申请号 JP19880218585 申请日期 1988.09.02
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SEKI KAZUHIKO;UMEHIRA MASAHIRO;SAITO SHIGEKI;TARUSAWA YOSHIAKI
分类号 H03L7/187;H03L7/199 主分类号 H03L7/187
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