发明名称 |
Arithmetic operation circuit |
摘要 |
An arithmetic operation circuit is provided which includes a logic processing circuit having a first metal-oxide-semiconductor-field-effect-transistor (MOSFET) column cascade-connecting a plurality of MOSFETs and a second MOSFET column cascade-connecting a plurality of MOSFETs. First and second ends of the second MOSFET column are respectively connected to first and second ends of said first column. A first power supply voltage is coupled to the common connecting point of the first ends of said first and second MOSFET columns. An amplifying circuit, including the grounded emitter type bipolar transistor, is provided such that the base thereof is connected to the common connecting point of the second ends of said first and second MOSFET columns.
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申请公布号 |
US4907184(A) |
申请公布日期 |
1990.03.06 |
申请号 |
US19870132368 |
申请日期 |
1987.12.14 |
申请人 |
HITACHI, LTD. |
发明人 |
NAKANO, TETSUO;IWAMURA, MASAHIRO;KURITA, KOZABURO |
分类号 |
H03K19/01;G06F7/50;G06F7/502;H01L21/8238;H01L21/8249;H01L27/06;H01L27/092 |
主分类号 |
H03K19/01 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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