| 摘要 |
PURPOSE:To operate the title circuit only by a clock of the same frequency as a bit rate of a reception signal by retarding the reception signal and distributing a signal after a delay and a signal before a delay in the same timing into plural memories separately and writing them. CONSTITUTION:A reception signal (data) and another reception signal (data) via a delay circuit 13 are inputted to a readout/write circuit 14. The data corresponds to an address '1' and is written in RAMs 11, 12 via a readout/write circuit 2. When the write is implemented up to 193 bitsX4 stages, a word corresponding to a 1st bit is read from the RAMs 11, 12 by the readout/write circuit 2, a data corresponding to the 5th bit is inserted to the word, the resulting word is written in the RAMs 11, 12 again and sent to a word synchronization detection circuit 15. Till a word corresponding to each bit is read till the coincidence of the word is implemented and the data insertion and re-write are implemented sequentially. Then the circuit is operated by using a clock having the same frequency as the bit rate of the reception signal. |
