| 摘要 |
PURPOSE:To construct a large capacity RAM from a CMOS gate array by constructing one transfer gate connected to a digit line from an N-channel type MOS transistor and the other from a P-channel type MOS transistor. CONSTITUTION:P-channel type MOS transistors 10-12, N-channel MOS transistors 20-22 are inverters constructed from transistors 10, 12 and transistors 11, 21, and their input terminals and output terminals are connected with each other to form a latch circuit. Transistors 12, 22 are a P-channel type MOS transistor, an N-channel type MOS transistor respectively and form transfer gates for connecting the latch circuit to a digit line, and gate terminals 43, 42 are select signal terminals of a RAM cell. The number of transistors for constructing a one bit RAM cell is three respectively, and the one bit RAM cell can be constructed from 1.5 basic cells so that the construction of a larger capacity RAM is enabled. |
