| 摘要 |
PURPOSE:To immediately transit the state to an objective state without inserting unnecessary cycles by determining the state of the following operation cycle by a late input signal settled in the present operation cycle. CONSTITUTION:Output signals 26 and 27 of constant generating circuits 13a and 13b correspond to a state D 23. A combination circuit 1 takes an input signal 3 and a state variable input signal 5 as the input and outputs an original output signal 15, an original state variable output signal 16, and a selector control signal 41 after a delay 42 of the combination circuit. This signal 16 corresponds to a state C 22, and in the normal case, transition 31 BC to the state C 22 is caused at the time of starting the next cycle. When the selector control signal 41 consists of two-bit signals S1 and S0 and a late input signal 8 consists of two-bit signals L1 and L0, an output W of a logic circuit 40 is generated in accordance with W=S1*L1+S0*L0. |
