发明名称 MULTIPROCESSING SYSTEM
摘要 <p>PURPOSE:To use independent clock signals in respective processing systems to perform multiple processings by coupling plural processing systems operated synchronously with respective clock signals in a digital device provided with the multiprocessing function. CONSTITUTION:A main data processing part 11 is operated synchronously with the main clock signal given from a main clock generator 12. Meanwhile, a tape recording processing part 19 is operated by the subclock signal from a subclock generator 20. When a flag FULL is sent from a buffer control part 18, a control part 11a temporarily stops data write from a RAM 15 to a FIFO buffer 17. Data is read out from the FIFO buffer 17 to the tape recording processing part 19 during this temporary stop, and the FIFO buffer 17 has a margin for data write. Then, the buffer control part 18 stops the output of the flag FULL, and the control part 11a restarts data write from the RAM 15 to the FIFO buffer 17.</p>
申请公布号 JPH0261752(A) 申请公布日期 1990.03.01
申请号 JP19880214124 申请日期 1988.08.29
申请人 CASIO COMPUT CO LTD 发明人 KOBAYASHI MASARU;MATSUI SHINICHI
分类号 G06F1/04;G06F15/16;G11B20/10 主分类号 G06F1/04
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