发明名称 FIELD EFFECT TRANSISTOR
摘要 PURPOSE:To decrease an ON-resistance without deteriorating the breakdown strength by a method wherein an insulated gate FET is formed in such a manner that the surface section of a drain region is made high in concentration and a region, whose conductivity type is opposite to that of the drain, is formed on the part of the drain region after the drain has been formed. CONSTITUTION:An N-type epitaxial layer 2 is provided onto an N-type semiconductor substrate 1, a P region 3 is formed through intrusion by implanting P-type impurity ions, and an N region 4 and a drain region surface section 5 are formed through the injection of N-type impurity of high concentration. Next, P-type impurity of high concentration is injected for the formation of P layers 7 and 8, moreover an oxide film 29 is deposited on the region 5, and then a source electrode 10 is provided, and a drain electrode 11 is formed on the rear. As the region 5 is made to diffuse laterally due to extrusion, a channel grows short and an ON-resistance decreases due to high concentration. And, a depletion layer of the P layer 8 is made to expand, so that the concentration of the electric field under a gate electrode 6 can be alleviated. By this setup, an ON-resistance can be decreased without deteriorating the breakdown strength.
申请公布号 JPH0260169(A) 申请公布日期 1990.02.28
申请号 JP19880211858 申请日期 1988.08.25
申请人 NEC CORP 发明人 KAYAMA CHIZURU
分类号 H01L29/06;H01L29/08;H01L29/10;H01L29/78 主分类号 H01L29/06
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