发明名称 |
Semiconductor memory cells and semiconductor memory device employing the semiconductor memory cells. |
摘要 |
<p>A spare memory cell (1) comprises a read FET (3) (Field Effect Transistor), a fusing FET (5) and a current fuse (7). The FETs (3, 5) are connected in series between a read data line (13) and a low voltage source (15). The fuse (7) is inserted between a series node of the FETs and a write data line (17). The fuse (7) is molten when data is written to the spare memory cell (1). By applying a power source voltage to a control electrode of the fusing FET and by applying a voltage that is higher than the power source voltage to the write data line (17), the fusing FET (3) is set to its secondary breakdown state. Under this state, a large current flows through the fusing FET (3) to cut off the fuse (7), thus writing data to the spare memory cell (1).</p> |
申请公布号 |
EP0355768(A2) |
申请公布日期 |
1990.02.28 |
申请号 |
EP19890115380 |
申请日期 |
1989.08.21 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
NARUKE, YASUO;MOCHIZUKI, THORU;IWASE, TAIRA;ASANO, MASAMICHI |
分类号 |
G11C17/00;G11C17/12;G11C17/14;G11C29/00;G11C29/04 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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