Timer channel with match recognition features.

摘要

A timer subsystem (21a) which provides a data processor (20) servicing the timer subsystem with the ability to inhibit the match recognition logic (150) of the timer subsystem while the processor is servicing the subsystem. The disclosed embodiment comprises a sixteen-channel timer subsystem (21a-21p) with a dedicated service processor (20). The service processor, under control of the micro-coded programs executing thereon, is capable of disabling a match recognition latch (150) in the timer channel currently being serviced. This feature provides the ability to prevent unwanted matches which occur while the service processor is updating the match register (132), for instance. Another feature of the timer subsystem is the inhibition of multiple matches to a single match register value by disabling the match recognition latch upon the occurrence of a match and re-enabling it only when the match register is written by the data processor.