Source follower field-effect logic gate (SFFL) suitable for III-V technologies.

摘要

A high speed logic circuit having extremely low propagation delays, suitable for implementation in III-V technology. A logic stage provides the desired logic function by combining a predetermined number of input FETs. The drains of the input FETs (13) couple to a pull-up FET (15) and form a first intermediate output (I) of the logic stage. The sources of the input FETs (13) couple to a pull-down FET (16) and form a second intermediate output (N) of the first stage (11). A second stage (20), or buffer stage, responding to the intermediate outputs of the first stage, provides sufficient drive to an output terminal of the logic gate to drive multiple loads (gates) coupled thereto. The second stage (20) includes a pull-down FET (21) responsive to the second intermediate output (N) of the first stage. The second stage (20) also includes alternative combinations of FETs (28) and diodes (22) to pull-up the voltage on the output terminal of the logic gate.