| 发明名称 |
Standard cell and standard-cell-type integrated circuit. |
| 摘要 |
<p>Disclosed is a designing method of a standard-cell-type integrated circuit obtained by utilizing composition of a standard cell (11) incorporating a signal delay function and employing the cell based on CAD and the like. Further, an arrangement example of a delay element (12) in the cell (11) is disclosed.</p> |
| 申请公布号 |
EP0355770(A2) |
申请公布日期 |
1990.02.28 |
| 申请号 |
EP19890115382 |
申请日期 |
1989.08.21 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA;TOSHIBA MICRO-ELECTRONICS CORPORATION |
发明人 |
WATANABE, HIROYUKI;KUDOU, TSUNEAKI |
| 分类号 |
H01L21/822;G06F17/50;H01L21/66;H01L21/82;H01L27/04;H03K19/0175;H03K19/173 |
主分类号 |
H01L21/822 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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