发明名称 |
Semiconductor memory device capable of selective operation of memory cell blocks |
摘要 |
A semiconductor memory device having a memory cell array constituted by a plurality of memory cell blocks includes a clock generator unit constituted by a plurality of clock generator sections, each of the clock generator sections corresponding to each of the memory cell blocks, and a block selector unit for selecting one of the clock generator sections in correspondence with the row address of a designated address. Accordingly, only a clock generator section corresponding to the selected memory cell block is operated by the designated address.
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申请公布号 |
US4905201(A) |
申请公布日期 |
1990.02.27 |
申请号 |
US19870059063 |
申请日期 |
1987.06.05 |
申请人 |
FUJITSU LIMITED |
发明人 |
OHIRA, TSUYOSHI;NAKANO, TOMIO |
分类号 |
G11C11/401;G11C7/22;G11C8/12;G11C8/18;G11C11/407 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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