| 摘要 |
A CPU has N-1 ports for concurrently making memory requests and transferring data using a cache with M partitions. Each partition includes a cache directory partition and a corresponding cache data store partition. Each port has a Partition Look-Aside Table (PLAT). Each PLAT has multiple entries that store the most-recent valid memory requests made by its CPU port. A PLAT entry includes a cache partition identifier, a control field, and a congruence-class address for locating associated data in the identified partition. Simultaneous cache accessing in up to N-1 different partitions may be made by N-1 CPU requests have PLAT local hits. The Nth port services global cache misses. An address switch simultaneously connects the CPU requests to up to N different partitions. A PLAT "local hit" occurs when a CPU request equals PLAT valid entry, enabling immediate accessing of the requested data in the identified partition. A PLAT "miss" generates a "global" request sent to all partitions. If the global request is found in any partition, a global "hit" occurs, and the data is transferred to the requesting CPU port through a data bus switch, and the port's PLAT is validated. If the global request is not found in any partition, a global "miss" occurs, which is sent to the system memory hierarchy for a data fetch; LRU circuits select a partition for receiving the data fetch, and a new PLAT entry is generated for the requesting port.
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