| 摘要 |
PURPOSE:To offer an input circuit suitable for the test of a PLA by constituting an internal node state forcing circuit effective for ease of function measurement of the PLA through a minimum number of circuits/terminals to the programmable logic array circuit (PLA) including regularly lots of internal nodes. CONSTITUTION:When a normal logic level is inputted to inputs V8, V28, the normal PLA operation is executed. When the level of the input V8 reaches the 3rd level (nearly 10V), a buffer 50 drives buffers BU1-BU7 of an external forcing circuit 1 to inactivate BV1-BV7. In this state, the logic of the inputs V1- V7 is set, nodes A1-A128 are selected at each item to measure and check inputs V21-V40. When the input V8 is brought into a normal level and the input V28 is set to the 3rd level, a buffer 51 drives the BU1-BU7 to inactivates BV21-BV40, the inputs V21-V27 control a decoder section 10 in this state to select the nodes A1-A128 at each node thereby measuring and checking the inputs V1-V20. |
