| 摘要 |
The logic circuit includes test data terminal in JK flip-flop circuit which comprises a first-stage logic circuit having two input terminals for receiving an input data resepctively. A second-stage logic circuit has an input connected to the output of the first-stage logic circuit and further has a clock signal input terminal for receiving a clock signal. There is a noninverted signal output terminal, and an inverted signal output terminal. The first-stage logic circuit operatively selects either the test data or the first and second input data in response to the enable signal, and the selected data is latched in the second-stage logic circuit in response to the clock signal.
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