| 摘要 |
PURPOSE:To obtain an integrated circuit with less chip area, i.e., high circuit integration by connecting an N-channel MOS transistor(TR) in parallel with a P-channel MOS TR of a conventional buffer and supplying inverted logic value to the gate of each TR. CONSTITUTION:An N-channel MOS TR 3 is connected in parallel with a P- channel MOS TR 1 and an inverted input of a gate of the P-channel MOS TR 1 is given to the gate via an inverter G. With an input terminal I at a low potential, an output of the inverter G goes to a high potential, then the TRs 1, 3 are turned on and the TR 2 is turned off and the output terminal O goes to a high potential. With the input terminal I at a high level, since the output of the inverter G goes to a low potential, the TRs 1, 3 are turned off and the TR 2 is turned on and the output terminal O goes to a low potential. |
